Design Considerations and Impact on Assembly

What are the most common design decisions that can have a negative impact on the PCB assembly and manufacture and how can we correct them during the design?

G.B.

Expert Panel Responses

An oft forgotten (until testing starts) design consideration is the spacings required by regulatory agencies (UL, VDE, etc) between “mains” and low voltage elements. This not only applies to spacings between traces on the board, but the spacings between and selection of components. Consider these design issues early on in the process, before you start board layout, if you are developing assemblies that must have regulatory agency approvals.

Also, consider thermal loading over the surface of the board(s). Do your best to spread evenly the (thermal) mass of the components over the area of the board. Concentrating heavy components in one area and lighter components in others can cause uneven heating during solder (reflow) which can really mess with the thermal profile required to solder properly, forcing the use special jigs or pallets to compensate. This may mean separating massive components (typically high power/large components) from lighter/smaller components onto different boards; don’t try to cram everything onto one board.

Paul Austen
Senior Project Engineer
Electronic Controls Design Inc

Paul been with Electronic Controls Design Inc. (ECD) in Milwaukie, Oregon for over 39 years as a Senior Project Engineer. He has seen and worked with the electronic manufacturing industry from many points of view, including: technician, engineer, manufacture, and customer. His focus has been the design and application of measurement tools used to improve manufacturing thermal processes and well as moisture sensitive component storage solutions.

These questions have a wide and long answers but i will try to provide some recommendations that helps to you to minimize errors or omissions during the design stage. In my experience, each variable or decision that we take on design stage, have a consequence on manufacturing.

I recommend first that fully know the class and usage of your product to determinate the design rules, the components and kind of the materials to use. this because combined with the design rules, will determinate the reliability and life of your product. The series of J-STD-001 to 006 can help to you to understand and select the right alloy or flux for your product and design according mechanical and chemical properties and characteristics of the solder and flux.

Once have an idea of the class and type of product you need design and manufactured, I fully recommend the series 2220 of IPC. This series is built around IPC-2221, Generic Standard on Printed Board Design, the base document that covers all generic requirements for printed board design, regardless of materials. From there, the designer chooses the appropriate sectional standard for a specific technology. All five sectional standards are included with the series: IPC-2222, Sectional Design Standard for Rigid Organic Printed Boards; IPC-2223, Sectional Design Standard for Flexible Printed Boards; IPC-2224, Sectional Standard for Design of PWBs for PC Cards; IPC-2225, Sectional Design Standard for Organic Multichip Modules (MCM-L) and MCM-L Assemblies; and IPC-2226, Sectional Design Standard for High Density Interconnect (HDI) Printed Boards.

Once you have all this and have a design, produce some samples. build some samples to validate the design and talks with the engineers of manufacturing to make a feasibility report. My finally recommendation is that.. If you will design a product, please create a multidisciplinary team (quality, engineering, manufacturing, purchasing, maintenance etc..) take all his recommendations and apply to you design if is possible.

In my experience, works separately and do not make a team, is the worst and most common error.

Andres Rojas
Engineering Director / Master IPC Trainer (MIT)
AMMSA Solutions

More than 20 years of technical experience in the electronics industry in roles ranging from Process & Project Engineer to engineering manager and Technical Applications Engineer for Latin Americas. IPC Master Trainer, International speaker and consultant.

A few of the most common issues include:

Ground planes directly connected to Plate Through Holes – failure to use spoke or traces to connect a pin to a ground plane greatly increases the amount of heat required to solder a particular pin on a connector or device. One pin may not get adequate hole fill when the soldering process is fine for every other PTH on the device or board.
Chip pad thermal imbalance – Instead of creating a pad some design just have a solder mask opening over a large copper plane. Especially in the case of small chips (0201-0402), one side will reflow well ahead of the other. The wetting force of the solder will begin to act on the side of the chip that went liquidus first and pull the chip in that direction, creating parts pulled to one side or tombstones.
Edge component clearance/board size – Parts too close to the edge of the boards that prevent conveyorized transport. This should be considered and panelization requirements documented on the fabrication notes. This also applies to boards not large enough for automated assembly. Panleization requirements should be included in the fab notes so that a bag of keychain sized boards are not received, and the stencils don’t need to be re-ordered when another PWB supplier is selected by purchasing.
Lack of fiducials – Designers still forget or “don’t have room” for fiducials. If there is actually no room, add them to the panelization as described above in the fab/gerber set so that the fiducial position is tied to the placements on the board.
Call out the applicable specification (IPC) on fabrication and assembly drawings – IPC-6012 and others cover a multitude of issues that cannot all be covered in the fab or assembly notes. Unless it is truly a special requirement let the applicable IPC specification (note the Class required) cover things like final finish, bow and twist, plating, cleanliness, etc.

Kevin Mobley
PCBA Engineering Liaison
General Atomics Electromagnetic Systems Group

Kevin has over 30 years of experience in process and manufacturing engineering serving in both EMS and OEM companies. Expertise includes all aspects of SMT as well as wave solder and CCA materials such as PCBs, solder material, and component finishes. Kevin has developed processes for thousands of assemblies from stencil printing to conformal coating and testing.

One item that I have experienced is to go straight into production without running a design for manufacturing or DFM. First, one thing to see your product on paper but that does not mean it will be easy to build. If this is happening to you I recommend inviting the design group to the production floor. Show them the capabilities and limitations of the manufacturing equipment including the capabilities and limitations of the assemblers. Second, sit down with the designer and discuss the project. I believe that the more you and your design team interact the easier the build.

Edithel Marietti
Senior Manufacturing Engineer
Northrop Grumman

Edithel is a chemical engineer with 20 year experience in manufacturing & process development for electronic contract manufacturers in US as well as some major OEM's. Involved in SMT, Reflow, Wave and other assembly operations entailing conformal coating and robotics.

Generally speaking, you should always strive to produce a board that is as simple as possible to manufacture and assemble. Always think about how you can relax your requirements, reduce the layer count to only what's necessary, and make a generous tolerance allowance for manufacturing errors.

For example:

For T.H vias, do mind the annular ring, a 5mil annular ring will be better than 4mil.
Likewise, a minimum thickness of 4mil trace will be better than 3mil.
In HDI design, staggered vias are much easier to build than stacked, copper-filled vias. And complex vias like microvia over buried VIPPO via - should be avoided.
Again in HDI, skip vias are something you might want to double-check with your manufacturer before using them. They may require expertise to plate and drill.
Assembly-wise, if you can avoid 0201 or smaller components - that would be easier to assemble.
In addition, leadless ICs like QFN / DFN must succeed to be assembled in their first pass in the reflow oven, if not, rework is difficult. So use them carefully only where needed.
Bow and twist of the PCB (non-flat PCB) can cause problems during assembly, for this we strive for a symmetrical stackup.
Cooper pour into SMD pads without thermal relief - can cause tombstoning or cold welds in small SMD parts - especially if one pad of the component is quicker to heat than the other.
Same with via in pad or microvia in pad. It can cause one pad to heat very slow compared to the others.
Invalid or missing component courtyard layer can lead to component's pads running over each other or missing required clearance.
As for BGAs, prefer the easier devices that have pitch of 0.8mm and above.

Guy Shemesh
General Manager
ePiccolo Engineering

Mr. Shemesh has Bsc. in E.E engineering and hands-on experience with electronics (schematics & layout) since 2004. He has designed dozens of multi-layer PCBs, HDI, RF, rigid-flex, etc., and had the honor for design reviewing veteran layout engineers several times as a consultant.

The factors that affect PCB design include drill holes, annular ring, trace widths, spacing between the traces, power planes on the edge of the board, and many more.

Drill holes:

For drill holes two significant aspects should be considered:

Aspect ratio: Maintain small aspect ratio. Ideal AR is 0.75:1 for vias.
Drill-to-copper clearance (drill to the nearest copper feature).
Minimum clearance = annular ring width + solder mask dam clearance
The typical drill to copper value is around 8 mils

Annular ring width: There should be enough annular ring width to establish a solid connection

Annular ring width = (Diameter of the pad – Diameter of the finished hole) / 2

For instance, if your pad diameter equals 22 mils and the hole diameter equals 10 mils, then the width is calculated in this manner: (22 – 10) / 2 = 6 mils.

Trace width:

Two important elements to consider:

Copper layer thickness: The default copper thickness for high current PCBs is around 1oz (35 microns) to 2oz (70 microns)
Cross-sectional area: Higher power PCBs need traces with a higher cross-sectional area.

To get an insight into the common design issues that adversely impact the board manufacture and assembly see 6 DFM issues designers should check before PCB manufacturing.

Amit Bahl
Director of Sales and Marketing
Sierra Circuits

Amit Bahl started to work at Sierra Circuits in 2006 where he formed strong relationships with his customers working with them on flex PCBs, HDI, controlled impedance, etc. In 2009, he was promoted Director of Sales and Marketing.

Given below are seven cases:

Replacement of an SMT passive device with another one for performance improvement. This has resulted in lower pad clearance (PCB layout was done for the previous device); a reflow soldering with this device may lead to tombstoning. Thus the device was replaced by manual soldering.
Replacement of a factory lead-formed Integrated Circuit (IC) device with user lead-formed device. The device was soldered but the shoulder needs to be shifted down so as to get accommodated in the slot. Additional staking was provided to overcome mechanical related issues.
To take care of component level redundancy, which was warranted after the manufacture of the PCB, vertical stacking with another device was adopted.
Copper exposure through the length of the shoulder of an IC due to improper annealing of the lead frame of the device, was taken care of by conformal coating.
Applied parylene coating to avoid moisture ingression into components through some holes/pits seen on devices.
Hardware connection was implemented externally on a PCB assembly due to anomaly seen in the micro sectioning of the coupon of the PCB.
Insufficient edge component clearance for Reflow soldering: Initially components on the edges were manually soldered and then done with a jig for carrying the PCB during reflow.

Dr. Oommen Tharakan Kuttiyil Thomas
Group Director
Vikram Sarabhai Space Centre

Dr. Tharakan’s experience is in the area of avionics package production, including reflow, test vector generation, formal verification of VHDL and verilog designs, screening of EEE components, quality control of electronic packages, and indigenisation of EEE components. Senior Member of the IEEE

An oft-overlooked consideration is testing. This states the obvious, but failure to incorporate testing access into board designs has a major impact on yield, and therefore productive throughput. Bonepile accumulations during functional test can be significantly reduced, if not avoided altogether, if mechanical test access, or the lack of it, is taken into account from the beginning of the design phase. Once a board is committed to CAD and resulting gerber files, it’s too late for test-based alterations until the next major revision spin.

A good starting point for basic test-related design rules is the SMTA TP-101E 2014 Testability Guidelines, available from the SMTA bookstore at smta.org. The TP101E Guidelines address topics such as probing/fixturing rules; flying probe guidelines; vectorless testing; IEEE 1149.1 and 1149.6 JTAG guidelines; Xray inspection rules; In-system programming guidelines; analog and mixed signal problems; built-in self test rules; AOI rules; and general physical layout considerations for all major test platforms such as ICT, Flying Probe, AXI, AOI, JTAG/Boundary Scan, and DFT rules of thumb.

Start with the theory advanced in the TP-101E Guidelines. Then talk to your test department or test engineering services provider for additional rules based on battle scars (real world experience). You won’t regret the effort.

Robert Boguski
President
Datest

Robert has 40 years of service in PCB and electronic system design, fabrication and assembly, test, and engineering, including X-ray/CT scanning for nondestructive failure analysis. He is on the SMTA Board of Directors and a columnist for Circuits Assembly Magazine.

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