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November 11, 2019

Considering Plasma Cleaning

We build microelectronic circuits with various small pitch flip chip die's and an assortment of passive components.

To improve underfill flow and better overall circuit cleanliness, we are considering plasma cleaning.

Is there any downside to plasma cleaning? I know in the past there were ESD concerns and we steered away from it.

T.G.

Expert Panel Responses

Plasma can be described as the 4th state of matter consisting of atoms, ions, radicals and electrons. Conceptually to create a plasma state, think of starting with a solid substance and continue to add energy and for each substance the state of matter moves from solid to liquid, then gas and finally with sufficient energy to a plasma state.

Your concern about ESD, especially for assembled devices / product is a real one. There are power limits that individuals put in place to help with ESD concerns. There are glass chambers and metal chambers, depending on models and manufacturer.

Thoughts on this is the metal chamber can absorb and discharge ESD/energies. If the PCB or substrate is to be cleaned in a plasma chamber prior to any assembly, I would say the ESD is not a concern. However if you have silicone and soldered locations in place already the plasma cleaning can redeposit onto surrounding surfaces and create additional soldering and Wire-bonding difficulties.

Back to ESD concerns, there is a technology called Atmospheric Plasma Surface cleaning, this might be a solution for assembled circuits with ESD concerns.

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David Cormier
Engineering Manager
Circuit Technology Center, Inc.
Manufacturing Engineer of 20+ years. Involved in Industries relating to all sectors of defense, Commercial product Industries, RF - Microwave and Semiconductor industries. Vast knowledge and experience relating Mil-STD’s, IPC-STD’s, EAI-STD’s, GEIA-STD’s, J-STD’s and MIL-PRF-STD’s.

There is no down side. We can use plasma cleaning.

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Amit Bahl
Director of Sales and Marketing
Sierra Circuits
Amit Bahl started to work at Sierra Circuits in 2006 where he formed strong relationships with his customers working with them on flex PCBs, HDI, controlled impedance, etc. In 2009, he was promoted Director of Sales and Marketing.

Underfill performance of the flip chip packaging only relies on the surface characteristics of the die and the substrate. Plasma treatment of the surface is important to improve both wettability and adhesion and realize a successful underfill process (low stress and delamination, high fillet height and wicking speed).

As for the ESD concern, plasma treatment is safe for most flip chip packaging. Most of our customers do not have concerns with the plasma process creating ESD issues. There will always be charged particles in a plasma but with equal number of negative and positive charges.

Typically, a direct plasma mode, where the substrate is exposed to glow discharge zone, is preferred for the underfill process for better performance unless the product is greatly sensitive to ESD, photo emission and/or UV light.

In this case, we would recommend, and only if necessary, the plasma downstream mode, also called ion free plasma (IFP) mode, where the substrate is placed downstream of the gas flow and is not directly exposed in the glow discharge zone. The downstream plasma process is believed to be a mild process. This is because most of the UV light and ions are filtered before the activated species can reach the surface of the substrate.

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Al Bousetta
Director of Marketing
Nordson March
Al holds a doctorate in joint physics and electrical engineering from the University of Manchester (UMIST) and has worked in semiconductor process and applications for more than 25 years. Al is the author of more than 30 technical papers.