Ask the Experts
October 14, 2019
Problems With Large Voids
I work at a very fast paced quick turn prototype house. Recently we had large voids on a 30mm x 30mm QFN Module. The voids were 50%-75%. Every single board failed.
I saw all of the solder paste prints, and the prints were perfect. The board was a simple 1.6mm thick PCB and we used the hotter version of our medium profile that covers 70% of our products due to placement density.
Most of our customers don't allow for full populated boards to pot with thermocouples to run profiles. What can I do to prevent huge voiding in the future on larger modules that are similar?
Expert Panel Responses
Voids causes and cures, is a popular question at many meetings. You mentioned that failures did occur but did not mention whether the failures were related to the voids. You also mentioned the hotter version of the profile was used and this could be one of the causes as it did not leave enough time to allow the flux volatiles to evaporate from the surfaces of the board and from within the solder paste.
If the solder paste reflows before the volatiles have had a chance to evaporate, those non metallic elements will remain within the solder joint, which will then increase the pressure within the solder joint and explode out of them once the pressure exceeds the strength of the solder, thereby creating voids in the solder joints.
The interaction between the solder paste and the via holes in the component location also has tendency create entrapment where those non-metallic material can create boiling pressure if you will and once they release, voids will also be evident. So keep track of the paste deposition process to make sure to minimize the amount of solder paste being place over the via holes.
Hence, check the oven profile, dry out the solder paste, and keep track of the results to see if any process improvements have occurred.
Vice President, Technical Director
At EPTAC Corporation, Mr. Lambert oversees content of course offerings, IPC Certification programs and provides customers with expert consultation in electronics manufacturing, including RoHS/WEEE and lead free issues. Leo is also the IPC General Chairman for the Assembly/Joining Process Committee.
- Use the hottest profile that the assembly can tolerate. Hot profiles typically improve wetting and better wetting reduces voiding.
- Use a thicker stencil. Using a thicker stencil creates more standoff under the component creating a larger channel for the flux vapors to escape.
- Use a window pane aperture pattern for the thermal slug. Cover 70% of the area with paste and have open channels between the individual paste deposits. The channels help the flux vapors to escape.
- Use a smaller solder particle size. Sometimes, all other things being equal, going to a smaller particle size reduces voiding (e.g. switching from a type 3 to a type 4).
- Increase the metal load of the paste. Higher metal load typically reduces the slumping of the solder paste during reflow. This helps to maintain the standoff.
- Explore different solder pastes. Some solder pastes are simply better at voiding than others.
Technical Support Engineer
Kay Parker is a Technical Support Engineer based at Indium Corporation's headquarters in Clinton, N.Y. In this role she provides guidance and recommendations to customers related to process steps, equipment, techniques, and materials. She is also responsible for servicing the company's existing accounts and retaining new business.
There are several possible contributing causes for the large voids, including:
Cause (1) can be mitigated by properly window-paning the print to allow better egress for gasses from the deposit as it reflows. Thermal vias, when present in the design, must also be considered. They can be both good (help with egress for volatiles) and bad (aid in collapse, which will squash voids and make them larger in area when viewed top-down).
- Lack of egress for gasses generated during reflow
- Higher than expected reflow temperatures
- Parts on first-assembled side, therefore exposed to two reflows
- A design that results in full collapse, resulting in a very thin solder joint
Cause 2 can be mitigated by proper profiling. Even if a production assembly cannot be profiled, we can usually identify a "proxy" assembly that has similar board and part mass density, and this is almost always adequate.
Cause 3 cannot be directly mitigated, unless you can change the order of assembly. An indirect mitigation is already in place if the reflow profile is optimized.
Mitigation of cause 4 can be difficult if we don't have control of the design. Only so much can be done with process change, and mainly this has to focus on how much and where we print the solder paste. We can avoid printing directly over the thermal vias, and by doing so minimize the amount of solder that is scavenged from our joint. In addition, we can balance the solder volumes in the thermal pad and peripheral joints such that we aren't squashing one or the other.
The specific paste being used can also have a great impact on the amount of voiding, however in many cases changing the paste is very difficult, and may have other unintended consequences. It's therefore not a solution to be approached lightly.
Fritz's career in electronics manufacturing has included diverse engineering roles including PWB fabrication, thick film print & fire, SMT and wave/selective solder process engineering, and electronics materials development and marketing. Fritz's educational background is in mechanical engineering with an emphasis on materials science. Design of Experiments (DoE) techniques have been an area of independent study. Fritz has published over a dozen papers at various industry conferences.
While these devices provide many benefits there are, of course some challenges as well. The most common of these challenges is voiding. The design of the QFN makes voiding one of its greatest assembly problems. When combined with a lead free process, the issue of voiding becomes even more problematic.
Voiding occurs readily on QFN's as volatiles become entrapped underneath the pad and unlike QFP's there are no leads and therefore no standoffs to allow for stress absorption and volatile escape. Large "lake voids" apparent in QFN below are typical of the type of voiding often seen with QFN devices. Profile alone seems to have little impact on the reduction of voiding without utilizing a lower volatile solder paste system, coupled with stencil design, thickness, and aperture reductions.
We have had success in reducing voiding by incorporating all of these measures into the assembly process. Utilizing a ramp-soak-profile with a higher soak temperature and time has shown further reductions in the quantity and size of the voids if stencil thickness and aperture reductions have been targeted first. The typical profile should ramp up to 190 degrees c from ambient in 75 - 90 seconds. Soak at 190 degrees c for 60 - 120 seconds. Continue to 20 degrees c above melting point of the alloy with a time above liquidus of 60 - 75 seconds.
Stencil Thickness In most cases it was determined that a 4 mil stencil offered significant improvement in reducing voiding over a 5 mil thick stencil.
Placement and Pad design Even and consistent placement pressure and depth is imperative. Component should be under tension on all sides to aid soldering. Moving the pads slightly out ward 15 -20% help maintain the tension and allows for some outgassing. Pads should not be necked down (narrowed) under component for single row QFNs to allow flow and to help ensure the traces do not fail during thermal cycling.
Aperture Reductions A variety of designs and percentage of reductions were utilized. We achieved the most consistent overall favorable results utilizing a 30-50% reduction with a window pane reduction design versus 100% Typical paste coverage prior to reflow was 50-80%. Your reduction design may be dependent of the type of assembly you are manufacturing. Keep in mind voids at vias can adversel affect performance on high speed RF applications and it may be necessary to mask or plug vias in order to prevent solder from flowing inside the via during reflow. Another option is to reduce the large ground plane pad in the center by utilizing a grid pattern of smaller pads in order to break it up or masking it off either will allow some out gassing between the pads under the component.
Solution Keys to successful implementation of the QFN into your designs are to control volume through stencil design, particle size reduction, paste volume reduction, and stencil thickness, which will minimize the volume of material which then must outgas the volatiles with the flux medium. Use a solder paste material which is specifically designed to address this issue. By altering the flux system to reduce volatile generation, voiding is lessened significantly.
Senior Applications Manager
Mr. Pigeon has been Senior Applications Manager with AIM Solder for more than 14 years, assisting customers with SMT Printing, Placement, Reflow, Troubleshooting, and Optimization as well as thorough knowledge of wave and hand solder applications. A combined 30+ years of electronics experience in both OEM and CM Manufacturing.
Poor "wetting" of the potting material is common, particularly to low surface energy polymers. This can result in poor bonding and voiding. Plasma activation raises surface energies and ensures good wettability, and more complete flow of resins onto almost all low energy polymer materials, including PTFE, silicone rubber and Kapton. Plasma treatment increases wettablility on polymers by chemically adding polar functional groups (chemically created in the plasma) to the surface.
The incorporation of oxygen groups into the surface of a polymer is indicative of polar functionality, and of a surface that is wettable by polar adhesives. This surface will have no skips, voids, blisters, or bleeding caused by incomplete wetting of the encapsulant. For other materials, (glass, ceramics, metals etc) a more wettable surface results primarily because oily surface residues are removed by the plasma.
Director of Technology
Demetri has been the Director of Technology for PVA TePla America since Oct 2004. Graduating from Trinity College, Ireland with a PhD in Surface Chemistry, he continued his research at UC Riverside as a Post Doctorate Research Fellow. In 2000 Demetri joined MetroLine Industries, a gas plasma equipment manufacturer in California, as a Process Engineer. In 2001 he took up a similar position with TePla AG in Munich, Germany, focusing on plasma applications in advanced chip packaging and flat panel displays. Demetri now focuses on the development of plasma surface modification processes for the Semiconductor, Device Packaging and life science industries.
I have 2 suggestions:
- Reduce the solder paste printed on the ground plane with window pane apertures letting the volatiles outgas during reflow.
- Adjust the reflow profile to less steep.
Vice President Technology
For over 18 years, Dr. Coleman has been the vice president of technology for Photo Stencil, working closely with customers to understand their printing requirements. His efforts have resulted in several new stencil products.
This is a common issue on the QFN packages - most of the times the issues are related to:
- Stencil aperture design and thickness - the volume of paste is critical as well as the design that will allow the gas to get out and not get trapped in the solder joint
- Oven profile - a profile that is too aggressive can still trap gases in the solder joints. Also try to use dedicated oven profile for each assembly as the generic settings can yield bad results
Engineering and Operations Management
Georgian Simion is an independent consultant with 20+ years in electronics manufacturing engineering and operations.
Contact me at firstname.lastname@example.org.