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March 10, 2026 - Updated December 3, 2025 - Originally Posted Removing Cleaning Residues Under BTC PackagesHow do you determine whether cleaning residues under BTC (Bottom Terminated Component) packages have been sufficiently removed in a no-clean processes? C.G. |
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Great question and the answer lie in reviewing the Section 8 of IPC J-STD.-001 which details the cleanliness requirements for electronic assemblies and especially how one must use a test protocol of using Surface Insulation Resistance (SIR TESTING) to gather the data necessary to validate the cleanliness state and what objective evidence one needs for validating and proving that the flux residues left behind or not left behind are benign and your electronic hardware is clean enough. This is a step by step guide and cleanliness specification to follow. There are companies out there that can perform this cleanliness testing for you that has the testing down to a science and helps build the objective evidence you need for future customer inquires or customer audits – I recommend a company called Magnalytix – out of Nashville Tn. - Please read SECTION 8 for all the details on how to validate underneath BTC components and gather the test data required to prove – objective evidence – that your material choices for soldering and flux materials and your processes for soldering and cleaning meet the Section 8 of J-STD-001.
VP Engineering Services STI Electronics Inc. Mark T. McMeen is STI Electronics Inc.ʼs Vice President of Engineering Services. He oversees the daily operations of the Engineering Services division of STI. He has over 18 years experience in the manufacturing and engineering of PCBs.
This is an excellent and highly relevant question, particularly given the increasing use of Bottom Terminated Components (BTCs) such as QFN and DFN packages in high-reliability applications. In a no-clean process, the objective is not necessarily complete residue removal, but rather verification that any remaining residues are chemically benign and do not compromise long-term electrical reliability. Due to the low standoff height and central thermal pad geometry of BTC components, residues may become entrapped beneath the package, making evaluation more complex. To determine whether residues have been sufficiently controlled, a combination of analytical and reliability-based methods is recommended. Ion Chromatography (per IPC-TM-650 2.3.28) is one of the most effective techniques for identifying and quantifying ionic species potentially trapped beneath BTC packages. For meaningful results, localized extraction of the BTC region is preferred, as whole-board extraction methods (such as ROSE) may not fully represent residues confined under low-standoff areas. Typical analytes include anions (Cl⁻, Br⁻, NO₃⁻, SO₄²⁻, weak organic acids) and cations (Na⁺, K⁺, NH₄⁺). However, numerical results must always be interpreted in the context of the product’s reliability requirements and operating environment. In addition to chemical analysis, Surface Insulation Resistance (SIR) testing under temperature and humidity bias conditions provides meaningful validation of electrochemical stability. Environmental stress tests such as THB (Temperature Humidity Bias) or HAST may further confirm that any residual chemistry does not pose a risk of corrosion or electrochemical migration. When necessary, multi-angle or 3D X-ray inspection and targeted cross-sectioning may help assess residue entrapment or verify interfacial integrity. Ultimately, in a properly controlled no-clean process, the critical question is not whether all residues are removed, but whether the remaining residues are electrically and chemically safe for the intended service life of the product.
Engineering Director / Master IPC Trainer (MIT) AMMSA Solutions More than 20 years of technical experience in the electronics industry in roles ranging from Process & Project Engineer to engineering manager and Technical Applications Engineer for Latin Americas. IPC Master Trainer, International speaker and consultant.
There is a destructive method to determine cleanliness under a BTC. This includes removal of the component and inspection for residues. You could also perform solvent extraction through immersion of the PCBA in a heated solvent suitable to dissolve the residues. Then have the solvent tested for various compounds of interest using ion chromatography (IC) or Fourier Transform Infrared Spectroscopy (FTIR). This will give an overall measure of cleanliness of the PCBA. Failure analysis labs may have other methods to assist with this.
Field Applications FCT Assembly Tony has worked in the electronics industry since 1994. He worked as a process engineer at a circuit board manufacturer for 5 years. Since 1999, Tony has worked for FCT Companies as a laboratory manager, facility manager, and most recently a field application engineer. He has extensive experience doing research and development, quality control, and technical service with products used to manufacture and assemble printed circuit boards. He holds B.S. and M.B.S. degrees in Chemistry.
Somewhat confused! The question "How do you determine whether cleaning residues under BTC (Bottom Terminated Component) packages have been sufficiently removed in a no-clean processes?" raises the question of "why are you cleaning a no-clean process?" The residues of a no-clean process by their nature are inert and require no cleaning. If you are actually washing your PCB you are wasting time & money.
President JSK Associates Based in. Northern California since 1971. Founded JSK Associates in 1979. Actively involved in soldering, cleaning, chemistries. 30 years experience in EOS/ESD control.
Great question C.G. Typically I like to perform Ion Chromatography (IC) extractions from components ( e.g., bottom terminated ) for both no clean as well cleaned ( e.g., IPA/H2O, DI H20, Saponified, etc.). Both references IPC J-STD-001 in conjunction with IPC-TM-650-2.3.28 require baseline IC testing for anions and cations. Unfortunately, they do not address residues left underneath components . But rather and area on the CCA for cleanliness. I tend to do a more localized extraction by using a syringe and applying a small amount of extraction solution to cover component in entirety while making sure not to contact adjacent components to minimize skewed test results. Also, I recommend you carefully remove( e.g., mechanically) some components ( BTC) to expose interface between PCB surface side and mating BTC surface for better IC extraction. Once complete I now have the following after no-clean processing: 1) IC data for whole CCA per IPC-TM-650-2.3.28 2) IC data localized for BTCs in question 3) IC data localized from removed BTCs Also, it is important to align electrical pass/fail test data( e.g., Flying Probe, ICT, EOL, etc.) from no-clean CCAs with IC limits from items 1-3 above to validate if no-clean is good enough as set-up. Again great question and I hope the above answers helps.
Fellow Raytheon Mark has over 35 years of experience in electronics fabrication, quality, and reliability while working for Raytheon RMD, IEC Electronics, GE, Motorola, ORS, etc. He has most recently taken the role as a Fellow at Raytheon in Tucson, AZ; prior to that, he established IEC Electronics Analysis and Testing Laboratories (IATL), LLC in Albuquerque, NM, for electronics and material analysis testing in the military, medical, and industrial industries. His expertise includes PCB, PCBA, components, and analytical and electrical analysis techniques.
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