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A Comparison of Thermal Cycling and Thermal Shock for Evaluating Solder Joint Reliability
The industry standard for accelerated temperature cycling, IPC-9701B, defines test conditions for characterizing solder interconnect fatigue. The document specifies a maximum cycling ramp rate of 20 °C/minute to avoid thermal shock conditions that can accelerate failure modes other than low cycle fatigue in the bulk solder.
Technical Paper
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Authored By:
Richard Coyle, Chloe Feng, Richard Popowich, Issac Becker
Nokia Bell Laboratories, NJ, USA
Dave Hillman
Hillman Electronic Assembly Solutions, IA, USA
Tim Pearson
Collins Aerospace, IA, USA
Michael Osterman
CALCE, MD, USA
Jayse McLean, Ranjit Pandher
John Deere, ND, USA
Joe Smetana
Nokia, TX, USA
Keith Howell
Nihon Superior Co., Ltd., Osaka, JP
Julie Silk
Keysight Technologies, CA, USA
Hongwen Zhang, Jie Geng
Indium Corp., NY, USA
Derek Daily
Senju Comtek Corp., CA, USA
Anna Lifton
MacDermid Alpha Electronics Solutions, NJ, USA
Morgana Ribas
MacDermid Alpha Electronics Solutions, Bangalore, IND
Raiyo Aspandiar
Intel, OR, USA
James Wertin
Heraeus Electronics, PA, USA
Jean-Christophe Riou
Safran Electronics and Defense, Valence, FR
Grace O’Malley
iNEMI, NC, USA
Madan Jagernauth
HDP User Group, International, TX, USA
Denny Fritz
Fritz Consulting, OH, USA
Shantanu Joshi, Jasbir Bath
Koki Solder America, OH, USA
Summary
The industry standard for accelerated temperature cycling, IPC-9701B, defines test conditions for characterizing solder interconnect fatigue. The document specifies a maximum cycling ramp rate of 20 °C/minute to avoid thermal shock conditions that can accelerate failure modes other than low cycle fatigue in the bulk solder. This investigation compares the performance and failure mode of two ball grid array (BGA) packages tested with cyclic ramp rates characteristic of thermal cycling and thermal shock. The accelerated temperature profile is from -40 °C to 125 °C for thermal cycling and thermal shock, with the cycling ramp rates approximately three times faster with thermal shock and with equal dwell times in cycling and shock.
The test matrix includes BGA packages fabricated with eutectic SnPb and near-eutectic SAC305 solder alloys as the performance baselines, and three high-performance solder alloys based on the SAC system but modified with additions of bismuth (Bi) and antimony (Sb). The failure data are reported as characteristic lifetime η (the number of cycles to achieve 63.2% failure), slope β, and cumulative 1% failure from a two-parameter Weibull analysis. Destructive cross-sectional analysis was used to characterize the solder microstructures before and after testing and the interconnect failure mode.
The results show that the thermal cycling ramp rate and the thermal shock ramp rate produced the same results quantitatively and the same failure modes. These findings apply to the two BGA components in combination with the five solder alloys used in the study. For these test conditions, omponents, and solder alloys, the same results were achieved in thermal shock compared to thermal cycling with a 30% savings in test duration.
Conclusions
Accelerated temperature cycling was used to evaluate the thermal fatigue performance (reliability) of solder interconnects in electronic assemblies. A review of the literature showed that increasing the ramp rate can decrease the cycles to failure significantly. In turn, this can shorten test times, reduce qualification cycles, and accelerate product development. However, fast ramp rates associated with thermal shock testing are not recommended typically because of the risk for accelerating failures other than the desired low cycle fatigue failure mode in the bulk solder.
This investigation was conducted to compare board level interconnect reliability and failure mode using test conditions representative of thermal cycling and thermal shock. The accelerated temperature profile was -40 °C to 125 °C with the cycling ramp rates approximately three times faster with thermal shock and with equal dwell times in cycling and shock. The test matrix was comprised of two ball grid array (BGA) test vehicles fabricated with five different solder alloys. The alloys included eutectic SnPb and SAC305 as performance baselines and three high-performance SAC-based alloys modified with additions of antimony (Sb) or bismuth (Bi).
Despite a significant disparity in ramp rate, there was an insignificant difference in reliability between thermal shock and thermal cycling. Reliability was quantified based on characteristic lifetime and 1% cumulative failure from on a 2-parameter Weibull analysis. These reliability findings were applicable to the five solder alloys and two BGA components.
The fast ramp rate in the thermal shock test generated the same fatigue failures in SnPb and SAC305 solder attachments as the slower ramp rate in the thermal cycling test. Thus, the reliability measured in thermal shock matched the reliability in thermal cycling and did so without altering the solder fatigue failure mode of SnPb or SAC305 solder attachments.
Solder fatigue was the predominant failure mode for the three high-performance alloys, but these alloys also showed susceptibility to interfacial and mixed mode failures in thermal cycling and thermal shock. These failure modes were not considered to be anomalous because they were reported in a previous study using these BGA components and alloys when tested with a ramp rate of only 10 °C/minute. Regardless of the occurrence of multiple failure modes with the high-performance alloys, the reliability measured in thermal shock matched the reliability in thermal cycling.
In conclusion, for these specific test conditions, components, and solder alloys, the same results were achieved in thermal shock compared to thermal cycling. In this investigation, a 30% savings in test duration was achieved in thermal shock due to faster ramp rates that shortened the cycle time compared to thermal cycling. This resulted in the number of cycles to failure being effectively the same in shock and cycling for each test cell. The authors caution the reader that this level of test duration improvement may not be typical due to the influence that test characteristics such as component type, dwell time, ramp rate, and failure mode have on the solder joint integrity.
Initially Published in the SMTA Proceedings
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Comments
In re-reading this study, the results, of course are well substantiated, but it would be particularly nice to know the conversion factors as relates to the real-world product lifetime expectations. Quite few applications have the temperature extremes of the test.
Jaye Waas, Renkus-Heinz
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