December 8, 2015 - Updated
December 2, 2015 - Originally Posted
Questions Regarding Underfill Options
We are being asked to apply a thermal compound layer of underfill under a SMT chip. Is there a standard that provides guidelines for too much, not enough, etc? If there is a hole on the secondary side of a CCA to apply this coating, what are some possible methods?
R.W.
|
There is IPC J-STD-030 Guideline for Selection and Application of Underfill Material for Flip Chip and other Micropackages. It provides all the information you need for your underfill process. To answer your second question; in all underfill methods I've worked with, the underfill was always applied from the top using automated equipment or directly onto the package prior to placement.
Edithel Marietti
Senior Manufacturing Engineer, Northrop Grumman
Edithel is a chemical engineer with 20 year experience in manufacturing & process development for electronic contract manufacturers in US as well as some major OEM's. Involved in SMT, Reflow, Wave and other assembly operations entailing conformal coating and robotics.
I would refer you the underfill manufacturer for their recommendations.
Kay Parker
Technical Support Engineer, Indium Corporation
Kay Parker is a Technical Support Engineer based at Indium Corporation's headquarters in Clinton, N.Y. In this role she provides guidance and recommendations to customers related to process steps, equipment, techniques, and materials. She is also responsible for servicing the company's existing accounts and retaining new business.
|
