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November 12, 2018

Insufficient Plated Hole Fill with Electrolytic Capacitors

We are having problems achieving the minimum hole of 75% on electrolytic capacitors using our wave soldering. What do you suggest?


Expert Panel Responses

You stated 75%,but you didn't say whether that is hole fill or 75% coverage of the soldersource side annular ring. Fortunately you can check similar items to clear upinsufficient solder problems. To achieve the75% fill depends on a few factors. First,solderability. If the plated hole is oxidized you will have difficultyachieving proper solder joints. How long have the boards been sitting openbefore you attempt to process? It's possible you may need to clean the boardsbefore you attempt to solder. See J-STD-003 for PCB solderability andIPC-CH-65B for cleaning advice. Second, Flux.Insufficient flux is another cause of insufficient solder. Whatever system youare using (bubble application, spray, ultrasonic, or proprietary application)must apply sufficient coverage to the areas being soldered. The flux also needsto be properly heated and activated to prepare the surface for soldering. Third, how isthe pre-heat on your wave solder? Don't underestimate the importance of thepre-heat. Not only does the pre-heat get the flux active in preparing thesurfaces, it also evaporated volatiles in the paste mix, and brings the entireassembly closer to the solder liquidus temperature. If you are attemptingto solder on a multi-layer board or especially a board with an heatsink/groundplane attached to the PTH in question, pre-heat is even more critical. Finally, rememberthat if the PTH is connected to a heatsink or ground plane, for an IPC Class 2assembly the criteria is 50% hole fill, not 75%.

Kris Roberson
Manager of Assembly Technology
Kris Roberson has experience as a machine operator, machine and engineering technician and process engineer for companies including Motorola, and US Robotics. Kris is certified as an Master Instructor in IPC-7711 / 7721, IPC A-610 and IPC J-STD 001.

Whatis the surface finish on the PWB, the lead to hole ratio being used and theaspect ratio/overall board thickness and how many internal planes interface ifay to the through holes?

Gerard O'Brien
S T and S Testing and Analysis
Gerald O'Brien is Chairman of ANSI J-STD 003, and Co Chairman of IPC 4-14 Surface Finish Plating Committee. He is a key member of ANSI J-STD 002 and 311 G Committees Expert in Surface finish, Solderability issues and Failure analysis in the PWA, PWB and component fields.

Wewould first recommend that you assess the solderability of the board andcomponent leads, at the same time check the hole-to-lead ratio. Too bigor small it will affect the capillary effect of the solder flow. Check tosee if you have a good preheat profile for the amount of flux you are using.

Terry Munson
President/Senior Technical Consultant
Mr. Munson, President and Founder of Foresite, has extensive electronics industry experience applying Ion Chromatography analytical techniques to a wide spectrum of manufacturing applications.

Haveyou tried high pressure? Also incorporation of voids is normally a sign that youare plating too fast.

Lee Levine
President, Consultant
Process Solutions Consulting Inc.
Lee Levine has been a Process Engineer and Metallurgist in the semiconductor industry for 30 years. He now operates his own company Process Solutions Consulting Inc where he consults on process issues and provides SEM/EDS and metallography services.

Possible cause of not reaching 75% fillet is High thermal copperlayer as plane connected to capacitor PTH. Solutions-1. Design: Execute DFM onthis PTH and see what is thermal value in this PTH.ie; Thermal Value = No of spokes X width of spokes XLayer Thickness, if it comes greater than 400milSq will sure here Designimprovement is required for this you need to change PTH solid type to Spoke orweb type where 4 spokes will be connected to PTH with a air gap which actuallyreduces thermal heat dissipation through this PTH. width of spoke will bedefined by current carrying through this PTH. Asshown in pic.
Ifyour design change doesn't work out due to cost implication, try solderingthrough selective wave soldering with a optimized soldering parameters liketime,temp or use selective wave pallet in wave soldering to execute this andoptimize. Since here design is the cause mitigating with process is somewhatchallenging. If this is one part, try to opt out from wave and do handsoldering with higher wattage soldering station 80W+ with Temp spec withincomponent manufacturer recommendation.

Subrat Prajapati
Supplier Quality Leader
Ge Healthcare
Subrat has 10 year of extensive experience in PCB assembly process optimizing for quality, process includes screen printing, wave, reflow. He has a copyright in stencil design published in Apex Expo2010 at Las Vegas US.

Contributing root causes of this defect can be one or more ofthe following:
  • Too many ties to inner ground planes, coupled with inadequatepre-heat - Non-thermally-relieved ties to ground planes are especiallyproblematic
  • Poor solderability of the specific components showing the defect
  • Flux penetration inadequate (especially problematic on thickboards)
  • Lead-to-hole ratio not optimized (typically a too-small holewith relation to the lead)
  • Very short lead protrusion (limits heat transfer to the lead)
  • Component is sitting tight to board, creating seal which gascannot easily escape - This can be a problem with electrolytic caps with plasticsleeves; as the component/board is heated, the air under it expands. Oncesoldering blocks the only points of exit, pressure builds, resisting flow ofsolder up the holes.
While the above listis not exhaustive, it covers the usual contributing causes. Remember that theremay be more than one contributing cause. Eliminating the biggest contributormay or may not adequately mitigate the problem.

Fritz Byle
Process Engineer
Fritz's career in electronics manufacturing has included diverse engineering roles including PWB fabrication, thick film print & fire, SMT and wave/selective solder process engineering, and electronics materials development and marketing. Fritz's educational background is in mechanical engineering with an emphasis on materials science. Design of Experiments (DoE) techniques have been an area of independent study. Fritz has published over a dozen papers at various industry conferences.

Hole-fill is a very common issue with wave soldering and hasbecome even more so with lead-free soldering.The cause of insufficient hole-fill is multi-faceted and can bedue to several causes summarized below.
  1. Board thickness, board finish, solderability of the finish forexample, thicker boards with OSP finish tend to be more challenging.
  2. Flux type and volume applied.
  3. Preheat sufficient to remove the flux solvents.
  4. Flux activity level and ability to sustain flux activity throughthe contact with molten solder.
  5. Wave process parameters such as immersion depth, contact timesand contact width.
  6. Lead-free or leaded solder and solder temperature.
To achieve good hole-fill choosing a flux designed for thespecific process is critical; usually a flux with a good activator package ableto sustain activity throughout the wave solder is important.Secondly insuring the flux is applied uniformly and into thebarrels to be soldered is key. This needs to be verified using thermal paper orother methods that insure the good flux penetration. The preheat has to be high enough to remove the volatiles in theflux but not too high as to cause premature de-activation of the flux.Activity is needed at the point of contact with molten solder toenhance hole-fill. To insure good hole-fill on difficult boards the immersion depthcan be increased to 75% of the board thickness.Also increasing contact time at the wave can help but here youneed to insure the flux is able to take the added heating. Oxidation levels of the parts to be soldered need to beunderstood to achieve good hole-fill. An example of difficult hole-fill would be an OSP board that sawx 2 reflow cycles prior to waving and that is relatively thick say 0.150" usingno-clean ROL0 flux in a lead-free wave.Here a flux designed for difficult hole-fill assemblies would berecommendable, fluxes designed with unique activator packages, able to takeslower conveyor speeds. A no-clean flux which has a slightly higher percent of solidscan also help. Water washable fluxes such ORH1 are more forgiving due to theiractivity levels but would require complete removal of residues after soldering.

Peter Biocca
Senior Market Development Engineer
Mr. Biocca was a chemist with many years experience in soldering technologies. He presented around the world in matters relating to process optimization and assembly. He was the author of many technical papers delivered globally. Mr. Biocca was a respected mentor in the electronics industry. He passed away in November, 2014.

For the typical thicknessprinted circuit board, .060 and .090" boards the hole filling of the platedthrough holes is a matter of solderability of the surfaces to be joined. I would recommend reviewingthe following conditions on the existing wave solder process as well asconducting solderability test on the components themselves. Check therequirements of IPC-J-STD-002, for the procedures for conducting solderabilitytesting of component leads. Here are some of the issuesto consider for plated through hole fill requirements.
  1. Lead to hole size ratio: The lead diameter should be .006 to .015 smaller than the finished hole size.
  2. Flux penetration from the fluxing operation: The flux must penetrate through the entire thickness of the printed circuit board.
  3. Proper preheat: Proper preheat of the printed circuit board going through the wave solder process.
  4. Solderability of the component lead: Check the solderability of the component lead materials. Electrolytic caps have a welded lead which after being welded may not be solderable.
  5. Heat sinking to the inner layers: Plated Through Holes are heat sinking to inner layers. This is also a condition occurs when the plated through hole are tied to the inner layers of the board and these connections prevents or reduces the heat in the holes and the solder solidifies are the inner layer level in the particular holes. This can be rectified by increasing the process temperature of the wave solder preheaters and slowing down the conveyor thereby increasing the contact time between the solder in the wave and the board itself.
  6. Depth of board in the wave: Lastly, if this is a thicker board, I would look at the depth the board is being processed through the wave solder system, many time the hydrostatic pressure of the molten solder can be used to move the solder up into the plated through holes.
Hopethis information is useful.

Leo Lambert
Vice President, Technical Director
EPTAC Corporation
At EPTAC Corporation, Mr. Lambert oversees content of course offerings, IPC Certification programs and provides customers with expert consultation in electronics manufacturing, including RoHS/WEEE and lead free issues. Leo is also the IPC General Chairman for the Assembly/Joining Process Committee.

Solder fill isdependent on Thermal balance, lead-to-hole ratio, solder tension andcleanliness. To check thermalbalance, ensure you have adequate preheat and solder temperature for yourrecommended alloy. Lead to hole ratio,is a function of design. You want to have better than 90% Lead to holdand possibly more if the PCB is .062 or thinner. Solder tension andCleanliness are a function of how you process and flux type used. If youhave followed recommended temperature and dwell times, your solder finish mayaffect this as well. There is no oneanswer to your question, but rather look at your soldering as a System, withdynamic variables. There might be a simple answer, but not necessarily...

Rodney Miller
Capital Equipment Operations Manager
Specialty Coating Systems
Rodney is currently Operations manager at SCS coatings, Global Leader in Parylene and Liquid Coating equipment. Rodney applies his BS in Computer Integrated Manufacturing from Purdue University, along with 20+ years of Electronic manufacturing and Equipment Assembly, to direct the Equipment business at SCS Coatings. "We provide unique, value added coating equipment solutions for our customers". Including conformal, spin and Parylene coating expertise.

It's really difficult to suggest something withoutknowing how the other components are wicking on the PCB and the solderablefinish of the circuit. What I would try first THIS IS ONLY TO TEST AND DO NOTRUN LIKE THIS, but apply a small amount of flux to the topside of the PCB andflux as normal and see if this helps the wicking this would generally indicatesomething is lacking in the flux area if you get much better wetting. If youcould supply more information then we may be able to pin point it for you

Greg York
Technical Sales Manager
BLT Circuit Services Ltd
Greg York has over thirty two years of service in Electronics industry. York has installed over 600 Lead Free Lines in Europe with Solder and flux systems as well as Technical Support on SMT lines and trouble shooting.

The challenging partabout wave soldering electrolytic capacitors is that this cap type is a powersupply filter, so the leads are connected to power planes and ground planes,most likely to internal layers of the PCB. Since the PCB is somewhatcolder than the solder, these internal layers are acting like heat sinks,pulling heat out of the barrel as the solder attempts to flow up the barrel.The best designs have thermal relief for these connections between the internalplanes and the power and ground pins, so less of the internal plane is directlyconnected to these power and ground pins. Adding a top side heater couldhelp, but it will not completely change the dynamics. Hand soldering isan option, enough said. You can also check the requirements, since theIPC has recently been discussing changing the spec for power and ground holefill to 50%. This is not usually to appealing to most engineers, but itis a possibility. This is one reason why there is a growing trend toreflow solder through hole components, but for electrolytics, you need toensure the component is rated to handle the peak temperature of reflow, whichfor SAC305 Lead Free solder is ~ 260C for 10-20 seconds. If you arestarting with a new design, and will run a new qualification process, you couldalso consider using a low temperature RoHS alloy such as SnBi as the alloy forreflow soldering the through hole components. Sn42Bi57.4Ag0.4 melts at138-140C, and the reflow temperature has a peak of about 180C. SMT1 andSMT2 can remain SAC305 (for example) and reflow at 240-245C, but then replacethe wave process with a third reflow, using the SnBi alloy. The lowertemperature third reflow will not disturb the SAC305 solder. Solderwashers would likely be needed, and choosing flux coated washers is preferred.

Paul J. Koep
Global Product Manager
Mr. Koep is responsible for product planning and technical marketing for the Preform Products at Alpha. He is the co-author of several patents in the areas of soldering applications focusing on reflow and alternative methods.

Reader Comment
So why is a poor fill a problem, particularly for electrolytic capacitors? Low PTH fill will typically not disrupt normal operation, but may cause temperatures to elevate in the vicinity of the PTH with the capacitor leads. The reason for the elevated temperatures is that reduced solder to PTH contact causes current crowding because the current density through these contact points can be very high. The high current densities can cause localized Joule heating which results in an elevated temperature at the contact region. In many cases the elevated temperatures may also cause localized melting and resolidification of the solder. Damage to the dielectric medium around the contact regions is also possible. In extreme cases, the leads or the cap, if displaced during a routine maintenance or handling procedure, may cause a total loss of contact with the PTH wall. Later, when the circuitry is re-energized, an instantaneous reconnection between the lead and the PTH can dissipate a lot of charge (typically through the negative lead), which is accumulated in the capacitor, and the high current creates lots of heat. The local temperature increases exponentially and surpasses the decomposition temperature of the surrounding epoxy/glass composite substrate (for FR4s). This temperature spike can also locally melt the barrel. There are recommendations on hole size, and the spec size may not always be sufficient for proper hole fill on dense components or components with large leads. The recommended hole size may be incorrect because it does not take into account board thickness and the effects of thermal load from multiple ground planes. Pin to hole ratio may be a good indicator for proper hole fill. Thermal loading (inner layer connections to the barrel) can have an effect on hole fill, the number of connected planes and more importantly, the placement of these planes (along the z) will effect thermal loads.
Bhanu Sood, CALCE, University of Maryland, USA

Reader Comment
We had similar problems regarding hole fill on a large assembly in a selective wave solder process and succeeded to achieve 80 to 100% solder fill. Due to time between preheat and soldering, the preheat temperature had dropped to below minimum temperature required for proper wetting. We broke up the solder program into 3 individual parts in order to reduce the time between preheat and actual soldering avoiding too large temperature drop after preheat prior to soldering. Improving from solder fill of 20-50% to 80% or even better was achieved. Of cause previous comments addressing application of thermal reliefs in PCB design, presence of thermal planes in different layers and good solder ability of PCB and component leads are required preconditions.
Frits Schoonbeek, Benchmark Electronics, Netherlands

Reader Comment
You must make sure your top side temp is correct prior to going over the wave. Also check to make sure there is enough flux being applied.
David Morse, Whelen Engineering

Reader Comment
The above comments assumed a cool joint +/or inadequate flux. I'm assuming you have tried more flux and slower and hotter preheats. We ran into this problem and the cause wasn't too little heat, but too much heat. The PTHs were not the optimum size for the small dia cap leads (PTH were too large) and the solder wetted, but then slumped back into the PTHs. We cooled down the board and got adequate fill. You can test this very easily by hand soldering a part. If it fills fine, then the assy is too hot. We found a top side temp of 100C was good for normal wave soldering. I don't recall what we had here but it was cooler.
Jerry Wiatrowski, General Dynamics, USA

Reader Comment
I am sharing my personal experience regard to insufficient plated Hole Fill or insufficient top side filling. The PCB solderability is critical. I used 4 different PCB vendor. One of the vendors had 100% top side filling, another vendor had about 85%. The last 2 had less than 10% top side filling. However, the last 2 had about 50% solder filling. The conclusion is that the PCB quality plays a critical role in solder filling.
Poh Kong Hui, LSI-montage Service, Singapore

Reader Comment
Today's Circuit Insight addressed hole fill for capacitors. Kris Robertson replied "Finally, remember that if the PTH is connected to a heatsink or ground plane, for an IPC Class 2 assembly the criteria is 50% hole fill, not 75%." This had changed in !PC-A-610F: Class 2 vertical fill for less than 14 leads is 75%. Capacitors have 2 leads, therefore fall into this category. 50% holds true for Class 2 for components 14 leads or more.
Ed Popielarski, Technical Services, Inc.