Modeling of Board Warpage During Solder Reflow

Josh Akman, Tyler Ferris, Micah Hernandez, and Michael Blattau
Ansys Inc
MD, USA

Excessive board warpage has long been known to cause issues during solder reflow of surface mount technology (SMT) components. These issues often manifest as manufacturing defects such as solder joint or via failures, as well as latent reliability failures. In this study, numerical methods are used to model board warpage during the soler reflow process. Multiple techniques are compared for modeling the printed circuit board (PCB) substrate with different levels of fidelity. Experimental warpage validation techniques are discussed. Inputs to the PCB modeling approaches and the results of the various modeling techniques are reviewed.

Several PCB modeling methodologies are reviewed with varying levels of pre-processing complexity, model fidelity, and computation time. Warpage measurements have mixed results with regards to correlation between the modeling methods and DIC measurements. Further testing, possibly with different samples, will help further refine differences in the methods. See the next steps section for more details. In-plane displacements from simulation show relatively good correlation with experimental measurements.

The trace mapping method is the one exception, which showed some divergence for both in-plane displacements and warpage above the glass transition temperature. This requires further investigation. The lumped model with uniform properties predicts little out of plane warpage for a bare board model.

Higher fidelity approaches, such as trace reinforcements and trace modeling, have the added benefit of localized stresses to identify regions with traces and vias containing high stresses. These are good for directional studies to identify areas of greatest concern. Additional characterization and refinement of the material models may be needed if these approaches are to be used for defining stress thresholds in copper traces and vias.