Blind vias that connect layer 1 to layer 2 or to layer 3 are an enabling technology for HDI (high density Interconnect) type boards. Via fill makes for a robust connection see fig 1 with no chance of any voids during assembly. Vias with 1:1 aspect ratio are common.
Successful via fill plating requires a specific electrolyte; the copper concentration is as high 50 - 60 g/L copper with low sulfuric acid at 30 - 60 g/L. This is combined with a unique organic additive combination with a prominent leveling component. The leveling component acts predominantly on the surface and suppresses the surface plating allowing the brightener and carrier combination to plate up from the bottom of the via. Ideally the solution movement must be vigorous and parallel to the surface (laminar flow); this ensures adequate leveler replenishment.
Understanding the principal of plating, the role of the additives, cell design and the critical role of "Pre- Treatment" are key for the successful running of the Via fill process day in and day out.
Microvia survivability through reflow must be established per IPC TM-650 2.6.27A using continuous 4-wire resistance measurement. There are many processes and PWB fabricators who claim microvia capability and form nice cross-sections of "good-looking" microvias, who do not realize that their microvias may open/reconnect during assembly reflow. Please provide data showing microvias survive the reflow thermal stress where 4-wire resistance measurement and surface temperature recorded to actual Forced Convection Reflow was completed.
