In this investigation a test matrix was completed utilizing 900 electrodes (small circuit board with parallel copper traces on FR-4 with LPI soldermask at 6, 10 and 50 mil spacing): 12 ionic contaminants were applied in five concentrations to three different spaced electrodes with five replicas each (three different bare copper trace spacing / five replications of each with five levels of ionic concentration).
The investigation was to assess the electrical response under controlled heat and humidity conditions of the known applied contamination to electrodes, using the IPC SIR (surface insulation resistance) J-STD 001 limits and determine at what level of contamination and spacing the ionic / organic residue has a failing effect on SIR.
The focus of this research was to determine at what level each ionic contaminant on nominal lead spacing in electronic hardware (IPC Class 2 and Class 3) will cause current leakage and corrosion problems to occur, using IPC J-STD 001 rev E SIR values for a pass/fail criteria.
This limit has a historical value of SIR for passing above 1.0e8 ohms of resistivity during exposure to SIR humidity conditions of 40oC/90%RH; a 5 volt bias with monitoring every ten minutes. The below levels of contamination correlate to good passing of SIR values for each of the individual ionic species.
Very good data for use in future failure analysis. I appreciate the spectrum of ionic species evaluated.
Excellent paper. With this paper one can understand why OEM manufacturers regardless of final finish ask for low SIR. SIR post cleaners are important to manufacturing electronics.
