Last Will and Testament of the BGA Void
This paper investigates the impact of voids in BGA and CSP components using thermal cycle testing per the IPC specification for tin-lead solder alloys.
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Authored By:
David Hillman, Dave Adams, Tim Pearson, Brad Williams, Brittany Petrick, and Ross Wilcoxon
Rockwell Collins, Cedar Rapids, IA, USA
David Bernard, Ph.D., John Travis, Evstatin Krastev, Ph.D., and Vineeth Bastin
Nordson DAGE, Fremont, CA, USA
Summary
The impact of voiding on the solder joint integrity of ball grid arrays (BGAs)/chip scale packages (CSPs) can be a topic of lengthy and energetic discussion. Detailed industry investigations have shown that voids have little effect on solder joint integrity unless they fall into specific location/geometry configurations. These investigations have focused on thermal cycle testing at 0°C-100°C, which is typically used to evaluate commercial electronic products.
This paper documents an investigation to determine the impact of voids in BGA and CSP components using thermal cycle testing (-55°C to +125°C) in accordance with the IPC-9701 specification for tin/lead solder alloys. This temperature range is more typical of military and other high performance product use environments. A proposed BGA void requirement revision for the IPC-JSTD-001 specification will be extracted from the results analysis.
Conclusions
The Coyle investigation found that macro voids reduce solder joint reliability by reducing the effective attachment area and that this geometric effect was independent of solder alloy composition. The study concluded that the dominant factor that impacts solder joint integrity was void location and not the void size or density of voids.
Initially Published in the SMTA Proceedings
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