Virtual Access Augments Test Coverage

Anthony J. Suto
Teradyne Inc.
North Reading, MA, USA

Increased pressures to reduce time to market and time to volume have forced many manufacturers of populated printed circuit boards to rely on capacitively coupled, un-powered, vectorless in-circuit test techniques to identify open pins on ICs and connectors. Unfortunately, faster signals and higher-density printed circuit boards (PCBs) have placed pressures on designers to reduce the number of test pads that provide electrical access for vectorless test techniques.

A powered-up test solution using boundary scan as the stimulus generator and a capacitive sensor plate for detection can address this loss of access. This virtual access method can quickly and effectively identify connectivity defects between boundary scan based ICs and other devices, including non-boundary scan devices, connectors, and sockets that lack physical test access.

This test approach employs a novel set of time domain auto-correlation and cross-correlation algorithms that eliminate many of the restrictions associated with existing frequency domain alternatives. More specifically, this test method does not restrict the operating frequency of the boundary scan's clock signal (TCK) or the number of scan cells in the boundary scan chain. Analyzing the temporal response of a single event pulse in the time domain by use of matched filtering eliminates the need to generate the narrow range of stimulus frequencies that traditional capacitive sensor plate methods require.

This virtual test method works with any boundary scan device that complies with the IEEE 1149.1, 1149.4 or 1149.6 standards. A discussion of this test method as well as recent field data, lessons learned and obstacles overcome while implementing this technique on a high-end computer server product at a high volume production facility are disclosed.

Powered opens allows for virtual access on high density PCB assemblies where there is limited board real-estate for test pad access and on high speed PCB signals that cannot tolerate the negative effects of electrical test pads.

Matched filtering from cross correlation offers the maximum possible signal to noise ratio in a noise-prone powered up environment and minimizes the opportunity for false calls on the production line. Production data from LGA1366 sockets on server boards confirms that the pulse based test method is very capable in terms of noise immunity, throughput, repeatability and false call rate.

When using time domain edge analysis instead of the more traditional frequency domain analysis, there are no restrictions on the number of scan cells in the chain. As a result, the time domain technique can identify common process defects and is compatible with present and future boundary scan compliant silicon devices.