Minimizing Voiding in QFN Packages

Seth J. Homer and Ronald C. Lasky, PhD, PE
Indium Corporation, Clinton, NY USA

According to Prismark Partners, the use of QFNs is growing faster than any package type except for flip - chip CSPs. Prismark projects that by 2013, 32.6 billion QFNs will be assembled worldwide, which represents 15% of all IC packages.

However, QFNs can be a challenge to assemble, especially when it comes to voiding. In most QFN assembly processes, solder paste is used as a means of attachment. This approach can be problematic, as excessive voiding often occurs due to the lack of standoff on the component and the high flux content of the paste. The addition of a solder preform can reduce such voiding by increasing the solder volume of the joint without adding flux volume.

Adding preforms to an assembly process is very easy. Preforms are packaged in tape & reel for easy placement by standard pick and place machines, right next to your components. The focus of this paper will quantify the preform requirements and process adjustments needed to use preforms in a standard SMT process. In addition, experimental data showing void reduction using preforms will also be presented

As stated, voiding under QFNs is attributed to flux entrapment and/or lack of solder in the joint. The addition of a solder preform dramatically increases the solder content without excessive flux. The additional solder density residing in the center of the pad also inhibits the development of a large void.

To minimize voiding design considerations should include:
Stencil Design: manufacturer recommended
Solder Preform Geometry: approx. 85% thermal pad dimensions and 50% paste thickness
Placement Parameters: increase placement pressure, muzzle selection
Flux Coating: required for solder preform/QFN interface
Reflow Profile: dependent/flexible