From the Single Chip to Wafer Integration

Gilles Poupon, Jean Charles Souriau, Herve Boutry, Jean Brun, Nicolas Sillon
CEA-LETI Minatec, Grenoble, France

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new System In Package (SiP) architectures, which combine a whole range of different technologies. In addition, due to the increasing complexity of systems, the introduction of new components like MEMS or RF components and the still growing pressure on size, performance and cost; a general trend is to put not one but several dies in a single package. However, cost is the critical issue in SiP Packaging as individual operations are currently necessary to complete each individual package. Taking into account all the developments that have been made to date on Wafer Level Packaging, it has been proposed to establish SiP at wafer level.

Companies that desire an "in-house solution" will prefer WLP because one of the benefits of the wafer level packaging is a simplified supply and value chain. Furthermore, for small companies (not IDM's), one of main consideration is to use generic technologies which can be applied on chips coming from different sources because they have no direct access to wafer manufacturing. To be compatible for chip multi-sourcing one of the most know examples on wafer level packaging is the fan-out wafer level structure This concept, proposed by major companies (Infineon, Freescale, ...), consists of rebuilding a wafer from heterogeneous Known Good Die (ASIC, sensor, memory, optic component etc.).After having established the current state of the art, the objective of this paper is to identify the various technological concepts and to give a focus on Chip in Wafer in Silicon technology developed at CEA-LETI.

As discussed initially, companies that want to develop "in-house" solutions prefer wafer level packaging because one of benefits is to simplify supply and value chain. Consequently with smaller companies, the main challenge is to process chips coming from different sources an without access to the wafer manufacturing For niche markets which require only small quantities of chips or heterogeneous components of various manufacturers, wafer level technologies remain interesting but difficult to implement due to a limited wafer availability.

The neo-wafer concept is really interesting because it makes it possible to select known good die, to integrate in a dedicated environment and tointerconnect at a conventional redistributive chip level. One of the main drawbacks is the susceptibility to deformation due to thermo-mechanical constraints. The technical approach, proposed by CEA LETI, consisting in using a silicon matrix and a positioning of the chips in cavities makes it possible to solve this difficulty.

It is possible to consider a 3D integration starting from reconstituted substrates comprising of heterogeneous chips. In this case, the simplest solution consists of building the intra-connections outside the chips. The process via belt developed is particularly adapted. All these developments in embedded wafer level packaging and 3D integration can be seen as an anticipation of future heterogeneous integration systems. Today, demand is increasing for a highly miniaturised system added to a low cost solution. The wafer level approach is probably one of the most promising solutions, the challenge is to be compatible with consumer market applications.