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Low Temperature Solder “Reverse Hybrid” Method
This paper will review the implementation of LTS “Reverse Hybrid”, which is the assembly of a ball grid array component with LTS solder balls to the motherboard.
Technical Paper
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Authored By:
Kevin Byrd, Dudi Amir, Yunfei Wang, Raiyo Aspandiar
Intel Foundry
OR, USA
Beihan Zhao, Karan Bhangaonkar
Intel Foundry
AZ, USA
Summary
Several trends in the microelectronics industry are increasing the value of reducing the surface mount reflow temperatures from those currently required for tin-silver-copper (SAC) solders. Reflow temperatures more than 200 ˚C have been shown to reduce micro-via life performance, increase the risk of memory cell retention issues with high density memory components, as well as lead to solder joint quality defects such as non-wet opens and solder ball bridging caused by component warpage. A growing body of literature has been dedicated to understanding and enabling tin-bismuth (Sn-Bi) based low temperature solders (LTS). While LTS solders allow significant reductions in reflow temperatures, concerns with risks such as reduced mechanical performance and bismuth electromigration, have slowed industry adoption.
This paper will review the implementation of LTS “Reverse Hybrid”, also known as backward compatibility, which is the assembly of a ball grid array component with LTS solder balls to the motherboard using SAC solder paste. While the temperature reduction benefits of LTS are lost with this approach, “Reverse Hybrid” can provide SMT yield benefits comparable to full LTS processing. As well, this process can allow an interested party to assess the performance of a Sn-Bi based component without the risk of converting the full motherboard to LTS. SMT yield and solder joint reliability results will be discussed as will techniques for the control of increased solder joint voiding which is the most significant SMT process risk.
Conclusions
Low temperatures solders (LTS) technology provides significant advancements in semiconductor package and system level process and reliability. Reverse hybrid LTS (RH-LTS) allows the already beneficial LTS technology to be easily integrated at system level by enabling a consistent SAC paste solution and reflow profile across all components on the system board. This paper demonstrates the compatibility and efficiency of RH-LTS SMT with advanced 2.5D and 3D package architectures. RH-LTS process fundamentals, failure mode analysis, as well as co-engineering dependencies such as package assembly materials, assembly process, package and board design, have been discussed. Key considerations observed for solder joint yield, quality and reliability, were identified to be optimum reflow profile, board paste material selection.
Key challenges for RH-SMT process such as voiding and solder bump bridging (SBB) have been reviewed. Guidelines to overcome these fails modes during technology design, definition and certification have been elaborated on. Key areas of research for expanding the scope of RH-LTS becomes further relevant with increased drive for higher system level performances and use of heterogeneous and complex package and system designs. RH-LTS is expected to be a key technology building block to enable the next generation of advance packaging architectures such as hybrid bonding, multi-level wafer stacking, omni-directionally interconnected package complexes and co-package optics.
Initially Published in the SMTA Proceedings
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