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Characterization of SIP Assembly and Reliability Under Thermal Cycles
This paper presents assembly challenges and reliability evaluation of Three-Dimensional Through- Mold Via and System in Package in fine pitch ball grid arrays.
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Authored By:
Reza Ghaffarian, Michael Meilunas
Jet Propulsion Laboratory, California Institute of Technology
Summary
This paper presents assembly challenges and reliability evaluation of 3D TMV™ (Three-Dimensional Through- Mold Via) and SiP (System in Package) in fine pitch ball grid arrays (FPGA). First, it presents the test matrix for various 3D TMV™ packaging assembly configurations and reliability characterizations performed under thermal cycling condition (–55°C to 125°C). The SiP test vehicles were configured with centrally located flip-chip (FC) die surrounded by eight chip scale packages (CSPs). The FC and CSPs, either with tin-lead or SAC305 balls, were assembled onto top of the FPGA interposer for subsequent assembly into a hybrid integrated configuration.
Mix hybrid assemblies were characterized by X-ray for solder-joint quality and by Shadow Moiré method for warpage characterization. The assemblies were then subjected to thermal cycling between -40C and 125C for evaluation of reliability and followed for characterization of failure mechanisms. The paper presents details of design, characterization by X-ray and Moiré as well as behavior of the SiP and 3D TMV™ assemblies under two different thermal cycling conditions.
Conclusions
This paper presented a comprehensive test matrix developed to assemble and evaluate reliability under thermal cycle conditions for a large number of advanced 3D TMV™ and SiP package assemblies. The 3D TMV™ and SiP assemblies were subjected to cycling profiles in the range of –55°C to +125°C and –40°C to +125°C, respectively. Characterization for quality assurance (QA) and failure analyses were performed by X-ray, optical images, and by X-sectioning evaluation.
For an accelerated thermal cycle profile of –55°/125°C, the three 3D TMV™ stack configuration assemblies—built with tin-lead solder at package and PCB levels, flux dip at package level and tin-lead solder at PCB level, and pre-stack package and solder at PCB—did not show failures after 200 cycles determined by daisy-chain resistance measurement. However, failures were observed at higher cycles and were analyzed by X-ray and X-sectioning.
For an accelerated thermal cycle profile of –40°/125°C, the SiP assemblies with either tin-lead or SAC305 solder balls did not show failures after 200 ATC determined by daisy-chain resistance measurement. However, failures were observed at higher cycles.
Possible reasons for early failures of SiP assemblies with underfilled CSPs were presented. Key parameters that paly roles in early failures are postulated to be: (1) the global CTE mismatches between FPGA and PCB, (2) local stiffness due to CSP on FPGA, and (3) higher warpage at the FPGA corner locations.
Further qualification tests are being performed by thermal cycling and characterizations to determine failure mechanisms and the reliability limitations of these advanced 2.5/3D electronic packaging technologies for high-reliability applications.
Initially Published in the SMTA Proceedings
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