Ask the Experts
September 6, 2023 - Updated
July 22, 2014 - Originally Posted

Concave Via Fillets Causing Problems

When we wave solder our circuit boards some of the vias have concave fillets giving them a dimple effect. The boards functions fine, but we are having problems when we test using our flying probe system. What can we do to create flatter fillets on via holes?


Expert Panel Responses

Maintain your pad size,but reduce the via size to the smallest diameter your board house can provide without driving-up cost.

Robert "Bob" Lazzara
Circuit Connect, Inc.
Bob has been in PCB design and fabrication since 1976. He has held elected positions with the SMTA, is a member of the MSD Council, has served as a committee member for various IPC standards and is a Certified IPC Trainer.

You could always try to reduce the dewetting causing the concave joints by speeding up the process just a little which will reduce the drag off or alternatively run the bath cooler.

Greg York
Technical Sales Manager
BLT Circuit Services Ltd
Greg York has over thirty two years of service in Electronics industry. York has installed over 600 Lead Free Lines in Europe with Solder and flux systems as well as Technical Support on SMT lines and trouble shooting.

In order to reduce or eliminate the dimples, we first need to list the root cause(es):
  • Solder shrinkage during solidification
  • Entrapped gasses that shrink as they cool, before solder solidification
These are the main drivers of the "dimpling" phenomenon. All solders shrink, to some degree, during solidification. This is different than CTE-related volume change, because it happens at a constant temperature as the solder solidifies(assuming a eutectic solder).

For example, the volume change of SnPb solder during solidification is approx. -4%. For an 0.062" board, that means that we might have a dimple as deep as 0.0025" due to solidification shrinkage alone. If we have entrapped gas bubbles prior to solidification, these will shrink in volume rapidly as the liquid solder cools from the soldering temperature toward the solidification temperature. Both of the above effects are important causes of the observed "dimpling."

We cannot do much about the first issue, since all solders exhibit this behavior to some degree. The second effect can be mitigated by minimizing the effects of trapped gasses. Low-solids fluxes and control of PWB quality and moisture content (to ensure that PWB outgassing is minimized) can help greatly. The probability is that even with all available mitigations in place, we will still have the issue to some degree.

At that point, we need to ask what we can do to make our test process less sensitive to the issue. Some possible actions are:
  • Use a test probe design that is less sensitive to the dimples.For example, make contact with the land as opposed to single-point contact with the solder.
  • Fill (not tent) vias to prevent soldering, leaving only the required test points open
  • Where space permits, use a test point land off the side of the via on the solder-destination side. This land will remain un-soldered and provide a clean area for probe contact

Fritz Byle
Process Engineer
Fritz's career in electronics manufacturing has included diverse engineering roles including PWB fabrication, thick film print & fire, SMT and wave/selective solder process engineering, and electronics materials development and marketing. Fritz's educational background is in mechanical engineering with an emphasis on materials science. Design of Experiments (DoE) techniques have been an area of independent study. Fritz has published over a dozen papers at various industry conferences.
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