October 8, 2015
ASSET ensures IJTAG IP re-use through interoperability with Cadence
ASSET and Cadence IJTAG interoperability ensures IP re-use for advanced SoC and system diagnostics
Product demos at International Test Conference show growth of ecosystem for IJTAG embedded instrumentation standard
Anaheim, CA, International Test Conference Booth 110 (October 6, 2015) -- At the International Test Conference (ITC) here this week, ASSET® InterTech (www.asset-intertech.com), a leading supplier of software and hardware debug, validation and test tools, and Cadence Design Systems Inc. (www.cadence.com) are demonstrating the interoperability of their IEEE 1687 Internal JTAG (IJTAG) tools, which enable the re-use of embedded intellectual property (IP) both internally on chips and externally onto system boards.
The key value of the IJTAG embedded instrumentation standard is the use of embedded IP in chips to debug, characterize and validate the internal operations of the devices themselves and then re-use this same IP to drive validation and structural tests externally from the host chip onto the circuit board for advanced system diagnostics.
"Several shared customers motivated our two companies to demonstrate the interoperability of our tools," said Tim Caffee, ASSET's vice president of design validation and test. "Both chip and system-level DFx engineers have found tremendous value in the ability to re-use embedded instruments and move back and forth diagnosing both chip operations and system performance. Plus the re-use of instruments already present in silicon holds great value for chips, systems and products throughout every phase of their lifecycles. We're very glad Cadence has joined the growing ecosystem of IJTAG tools."
ASSET's ScanWorks® IJTAG tool complements the Cadence® Encounter® Test tool's ability to insert various types of IJTAG-compatible IP into silicon. Internally to the chip, this IP might monitor operating parameters or confirm the functionality of the device. Externally from the chip, embedded IJTAG IP could be re-used to drive data across serdes buses for performance testing or to analyze the system's operating margins. Another example would be a logic built-in self-test (BIST) controller that acts as an embedded instrument for validating internal digital logic. It could then be accessed from the circuit board to retest the logic within the chip.
"The Encounter Test tool delivers a comprehensive design for test (DFT) and automated test pattern generation (ATPG) solution for today's complex ICs and SoC designs," said Paul Cunningham, vice president of research and development in the Digital and Signoff Group at Cadence. "As chips and, particularly, SoCs, have become more complex, embedded JTAG-accessible instruments are taking on a greater role in characterizing the internal operations of these devices. The interoperability between the Encounter Test tool and ASSET ScanWorks allows our mutual customers to re-use the IP for external debug, validation and test, which increases the value of the IJTAG IP."
About ASSET InterTech
ASSET InterTech (www.asset-intertech.com) is a leading supplier of tools to debug, validate and test software and hardware. The company's SourcePoint software debug and trace platform and ScanWorks® platform for embedded instruments work in tandem to give engineers real insight from code to silicon. SourcePoint is a best-in-class, powerful debugger that includes advanced trace tools to gather data from code and quickly debug complex embedded software systems. ScanWorks controls instruments embedded in chips to test and validate chips and circuit boards. Together they empower engineers with tools and technology for the entire life-cycle of a system, beginning with software and hardware development, on to design validation, through software/hardware integration, and eventually testing the product in manufacturing and field service. ASSET InterTech is located at 2201 North Central Expressway, Suite 105, Richardson, TX 75080.
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