ASSET's ScanWorks platform for embedded instrumentation remains the only toolset for Intel®’s Interconnect Built-In Self Test (IBIST)

Richardson, TX – ASSET® InterTech (http://www.asset-intertech.com/), the leading supplier of open tools for embedded instrumentation, has enhanced its validation and testing tools for Intel®’s future platforms. In this arrangement, ASSET’s ScanWorks® platform for embedded instruments will continue to support Intel®’s Interconnect Built-In Self Test (IBIST) technology which is embedded in the chip company’s processors and chip sets, and ScanWorks will provide a comprehensive validation solution for high-speed input/output (I/O) on Intel platforms.

"For six years we’ve been the industry’s only provider of IBIST tools. During that time, we’ve gained a great deal of trust from Intel®. Both ASSET and Intel® have benefited from the relationship," said Tim Caffee, ASSET’s vice president of design validation. "We look forward to continuing this support with future Intel® platforms. Additionally, the ScanWorks platform’s I/O instrumentation tools are expanding beyond Intel®'s QuickPath Interconnect (QPI) high-speed serial bus to provide manufacturers with an expanded high-speed I/O validation solution."

The ScanWorks validation tools for Intel® IBIST include functionality to perform bit error rate testing (BERT) as well as margining tests. In validation applications, these types of tests can be employed to validate that the high-speed serial I/O buses on a circuit board design will perform as expected before the design moves into high-volume manufacturing. According to Caffee, ScanWorks’s next-generation tools will support all major high-speed I/O buses, including QPI, PCI Express (PCIe), Direct Memory Interface (DMI), and Double Data Rate 3^rd Generation (DDR3).

"With increasing signaling rates in modern platform designs, IBIST tools such as the ASSET ScanWorks platform have become necessary for the verification of those interfaces," said Gene Pitts, Data Center Platform Application Engineering (DCPAE) Director at Intel. "More effective solutions for the verification of complex design challenges allow the industry to focus on other value-add aspects of their platform designs without risking design robustness."