ScanWorks® integration into Cadence Encounter Digital IC Design Flow to provide deeper view into complex, packaged chips

Richardson, TX – ASSET® InterTech Inc. is working with Cadence® Design Systems, Inc. of San Jose, Calif., to integrate ASSET’s ScanWorks platform into the Cadence Encounter Digital IC Design flow. The integration will enable design and test engineers to embed instrumentation tools into complex, finished system-on-chip (SoC) and system-in-package (SiP) devices, providing deep analysis and test of these chips even after installation in the final product. The project kicks off immediately following the recent addition of Asset InterTech into the Cadence Connections partner program.

The Cadence Connections Partner Program is available to makers of third-party software products that complement Cadence solutions and further enhance industry interoperability. Membership in the Cadence Connections program provides ASSET with access to Cadence software, documentation and support capabilities to facilitate the integration of ScanWorks’ embedded instrumentation tools into Cadence’s IC design, test and diagnostic flows. Cadence’s leadership in board and SiP package design will be leveraged to address the growing challenges of SiP and multi-chip module (MCM) device testing and diagnostics. Initial applications will provide tools and flows that support the preliminary IEEE P1687 Internal JTAG (IJTAG) standard.

“We are seeing a rapid confluence of our technology with EDA systems, such as Cadence Encounter Test,” said Alan Sguigna, vice president of sales and marketing at ASSET. “Our strategic emphasis on open embedded instrumentation tools for design validation, test and debug can accelerate the chip verification and test process and enhance yields. This is especially true for the denser chip packaging techniques such as complex system-on-a-chip (SOC), system-in-package (SiP) and package-on-package (PoP). Cadence’s end-to-end solutions and diagnostics leadership positions the company to address these challenges.”

“As chips become more complex, including not just one but several entire systems in a single package, the ability to analyze and test deep within the device creates enormous benefit,” said Steve Carlson, vice president of IC digital at Cadence. “The collaboration to integrate ASSET’s ScanWorks software is expected to provide an automated data acquisition and data analysis capability that fundamentally turns on the light for chip designer and test engineers.”

ScanWorks® – The Embedded Instrumentation Platform

ASSET, through its ScanWorks platform, is applying the experience it has gained from two decades as a leading supplier of boundary-scan test tools utilizing JTAG access to the development of open embedded instrumentation tools. The boundary-scan infrastructure that is embedded into chips and circuit boards is one of several technologies that can form the basis for an embedded instrumentation toolset. In recent years, ASSET has significantly enhanced its ScanWorks platform with embedded instrumentation capabilities such as CPU-emulation functional test, signal integrity analysis utilizing embedded Intel® IBIST (Interconnect Built In Self Test) technology and others.

With its advanced automation, data acquisition and data analysis features, ScanWorks will continue as a leading platform for structural boundary-scan test. It has become the boundary-scan system of choice for practically all major communication and defense/avionics suppliers, including Cisco, Ericsson, Motorola, Alcatel-Lucent, Tellabs, Huawei, Raytheon, Rockwell, Lockheed Martin, BAE, ITT, Northrop Grumman, Smiths and others. In addition, ScanWorks’ adoption by companies like Microsoft for its Xbox 360 video game console and Delphi for its automotive electronics demonstrates that ScanWorks will continue its leadership as boundary scan proliferates in computers, set-top boxes, consumer electronics, industrial controls, automotive and other industries.